The present invention relates to an all-digital phase-locked loop (PLL). More specifically, the present invention relates to an improved all-digital phase-locked loop, which provides the advantages of lowered cost, high stability, and can be implemented with a very narrow loop bandwidth.
A phase-locked loop (PLL) is an electronic circuit for locking an oscillator in phase with an input signal. In other words, a PLL is an electronic circuit for synchronizing, in frequency as well as in phase, an output signal with a reference signal. A PLL can act as a demodulator to demodulate a carrier frequency, or it can be used to track a carrier or synchronizing signal whose frequency varies with respect to time.
PLLs have found a variety of important applications in, for example, communication systems, computers, television engineering, etc. In general, PLLs can be classified, based on its method of implementation, into three main types: analog, mixed digital/analog, and all digital PLLs. A basic analog PLL consists of a phase detector and a low pass filter with a feed back loop closed by a local voltage-controlled oscillator (VCO). The phase detector detects and tracks small differences in phase and frequency between the incoming signal and the VCO signal, and provides output pulses that are proportional to the detected difference. The low-pass filter removes alternating current (ac) components to provide a direct-current (dc) voltage signal to drive the VCO. The input voltage will act to change the output frequency of the VCO to that of the input signal. The phase detector and low-pass filter function as the mixer in a general feedback loop. The output is driven in the direction that will minimize the error signal, such as in frequency. Accordingly, the loop tends to drive the error signal back toward zero frequency. Once the two frequencies are made equal, the output from the VCO will be locked into the input signal, and any phase difference between the two signals will be controlled.
Recently, all-digital PLLs have been developed which provide several advantages over the analog PLLs, including: (1) high yield rate from the IC process; (2) low cost, (3) high stability; (4) can be implemented without external components, such as VCXO, loop filter, etc.; (5) can be implemented with a very narrow loop bandwidth; and (6) can be implemented in a single PLD, thus fostering system development. Some of the most commonly used digital PLLs include SN54LS297 and SN74LS297, both are available from Texas Instrument. The two chips are essentially identical in specification except that the former can operate at a broader temperature range (xe2x88x9255xc2x0 C. to 125xc2x0 C.) than the latter (0xc2x0 C. to 70xc2x0 C.).
While the all-digital PLLs provide many advantages over their analog counterparts, there is also a very important drawback: they need a substantially higher frequency sample clock than the input clock to divide the input clock period into a fractional of the unit interval (UI). The extent to which the sample clock must be faster than the input clock depends on the maximum permissible output jitter. For an E1-rated output (2.048 M Hz), if the maximum allowable output jitter is to be controlled below 1/32 UI, the conventional all-digital PLL would need a sample clock with a frequency as high as 131.072 M Hz or 65.536 M Hz. The requirement of such a high frequency sample clock can substantially increase the design complexity and the cost thereof.
In an article entitled: xe2x80x9cPHDPLL for SONET Desynchronizerxe2x80x9d, by Chii-Min Loau and Ji-Tsu Wu, it is disclosed a phase-hopping digital PLL (PHDPLL) for high-speed desynchronization which provided very narrow bandwidth (below 1 Hz). The PHDPLL included the conventional EXclusive-OR (EXOR or XOR) phase detector and a phase-hopping digitally controlled oscillator (PHDCO). The PHDPLL uses the delay time of a basic gate (e.g., a buffer or an OR gate) to cause a phase hopping and thereby a phase step, and does not require a sample clock which is required by a conventional all-digital PLL. However, the gate delay utilized in the PHDPLL is highly susceptible to variations due to fluctuations in the local temperature, process and voltage. The variation in the gate delay can range from as high as twice as much as the designed value to as low as one-half of the designed value. Such a large variation in the intended gate delay can result in failures in attempting to acquire the lock-in, or generate a large output jitter.
Because of the above mentioned shortcomings, there exist needs to design an improved all digital PLLs which can be implemented with a sample clock operating at a substantially lower frequency than that is required in the current system, and exhibit the required stability which will be independent of temperature, process, voltage and other environmental variations.
The primary object of the present invention is to develop an improved all-digital phase-locked loop. More specifically, the primary object of the present invention is to develop an all-digital phase-locked loop which can be implemented with a sample clock operating at a substantially lower frequency that what would be required by the conventional all-digital phase-locked loops. The all-digital phase-locked loop disclosed in the present invention also exhibits excellent stability which is independent of temperature, process, voltage and other environmental variations such as the initial state. With the improved all-digital PLL disclosed in the present invention, the sample clock can be reduced to xc2xd or xc2xc of that required of a conventional all-digital PLLs, while achieving the same or even improved performance at a reduced manufacturing cost. Another distinctive advantage of the improved all-digital PLL disclosed in the present invention is that, because of its excellent stability, the loop""s performance can be emulated in advance. This greatly facilitates the implementation and design of the loop, ensures its performance, and keeps the cost down.
In the all-digital PLL disclosed in the present invention, a delay line, which is structurally similar to a pipe line, is designed to provide a plurality of phase-different clocks. The improved all-digital PLL of the present invention comprises five main components: a divide-by-N counter, a divide-by-M counter, a phase-frequency detector (PFD), a K-counter, and a digital control oscillator (DCO). The divisors N and M must be properly chosen in accordance with the clock frequency and the intended application(s), so as to result in the smallest frequency variation for PFD inputs. The PFD is provided to compare the phase and frequency of the two incoming signals xcfx86in and xcfx86out. The output signals from the PFD depend not only on the phase error but also on the frequency difference xcex4xcfx89 (which equals to xcfx89inxe2x88x92xcfx89out). The PFD can be constructed from two D-type flip-flops, whose outputs are denoted as xe2x80x9cUPxe2x80x9d (up) and xe2x80x9cDNxe2x80x9d (down), respectively. Typically, the outputs of a PFD are initialized at xe2x80x9czero statesxe2x80x9d. If the two input signals are exactly in phase, the positive edges of these two input signals will occur at the same time. Hence, their effects are canceled against each other, and the output from the PFD will be zero until a different situation is detected. When the two input signals are out of phase, the PFD will detect the phase error, which would range from xe2x88x922xcfx80 to 2xcfx80. The output signals xe2x80x9cUPxe2x80x9d and xe2x80x9cDNxe2x80x9d from the PFD are sent to the K-counter for adjusting the frequency of the loop""s output. When the total pulse width of the xe2x80x9cUPxe2x80x9d signals is greater than that of the xe2x80x9cDNxe2x80x9d signals, the frequency of the loop""s output will be reduced (i.e., slowed down). On the other hand, when the total pulse width of the xe2x80x9cUPxe2x80x9d signals is smaller than that of the xe2x80x9cDNxe2x80x9d signals, the frequency of the loop""s output will be increased (i.e., sped up).
The K-counter operates in cooperation with the DCO to produce a signal which is fed back to the PFD through the divide-by-M counter. Included in the K-counter are an xe2x80x9cupxe2x80x9d counter and a xe2x80x9cdownxe2x80x9d counter. The K-counter works as a digital loop filter. A xe2x80x9ccarryxe2x80x9d output (CA) is generated from the up counter, and a xe2x80x9cborrowxe2x80x9d output (BO) is generated from the down counter. The two output signals, CA and BO, are sent as inputs to the DCO. If the DN output from the PFD is active, this enables the down section of the K-counter. When the K-counter is under flow, this will produce a xe2x80x9cborrowxe2x80x9d pulse. The borrow pulse will force the DCO to select a phase-leading local clock, and the loop""s output is xe2x80x9cadvancedxe2x80x9d. On the other hand, if the UP output from phase detector PFD is active, then this signal will enable the up counter section of the K-counter. When the K-counter is over flow, this will produce a carry pulse. The carry pulse will force the DCO to select a phase-lagging local clock, and the loop""s output is xe2x80x9cdelayedxe2x80x9d.
In the all-digital phase-locked loop of the present invention, the value of K in the K-counter is an important parameter. If the value of K is too small, then the K-counter will recycle very often, thus generating an undesirably high frequency of carry and/or borrow pulses. This means a high frequency phase hopping of the loop output and a high frequency in the output jitter. On the other hand, if the value of K is too small, the loop""s cut-off frequency will be undesirably too low and the lock-in range is small, thus resulting in a prolonged tracking process.
One of the key elements of the DCO of the present invention is a delay line arranged into L stages (i.e., an L-staged delay line). Other elements of the DCO include an up-down counter and a multiplexer. The delay line, which is structurally similar to a pipeline processor, provides a set of phase-different clocks for the DCO to implement a phase-hopping action. The up-down counter accepts the carry and borrow signals from the K-counter and outputs an address to the multiplexer to thereby select a corresponding clock from the set of phase-different clocks, which are provided as outputs from the delay line. In the simplest case, the delay line consists of L phase-different clocks and each pair of neighboring local clocks has a phase difference of xcfx86. Each time the carrier pulse forces the multiplexer to select the phase lagging local clock, the loop""s output will be delay by 1/L cycle. Likewise, each time the borrow signal forces the multiplexer to select a phase leading local clock, the loop""s output will be advanced by 1/L cycle. In this construction, the value of xcfx86 must satisfy the following relationship:
xcfx80 less than xcfx86L less than 2xcfx80
The phase delay designed in each stage (of the L stages) has a very significant influence on the loop""s output jitter. In order to reduce the amplitude of the output jitter, the value of xcfx86L should preferably be as close to 2xcfx80 as possible. To achieve this, in a preferred embodiment of the present invention, the delay line is implemented using a series of flip-flops and a sample clock having a frequency that is L/2 times the frequency of the loop""s output. Thus, with a 32-stage delay line (i.e., L=32), if the maximum permissible output jitter is 1/32 UI, then a sample clock with a frequency 8 times of UI will satisfy the requirement. Therefore, to implement a locked loop for an E1/T1 rate, the present invention can satisfy the requirement by using a sample clock having a frequency of 32.768 M Hz/24.704 M Hz (i.e., using a 32.768 M Hz/24.704 M Hz oscillator). Because a much slower sample clock is required, the present invention is much economical than the conventional all-digital phase locked loops. Furthermore, because the present invention uses a novel design involving a simple delay line to provide the phase-different clocks, it exhibits excellent stability and its performance is unaffected by temperature, process, voltage and/or other environmental variations.